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INTEGRATED CIRCUITS
DATA SHEET
TDA9885; TDA9886 I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
Product specification Supersedes data of 2002 Mar 05 2003 Oct 02
Philips Semiconductors
Product specification
I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
CONTENTS 1 2 3 4 5 6 7 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.14 8.15 8.16 9 9.1 9.1.1 9.1.2 9.2 9.2.1 9.2.2 9.2.3 9.2.4 FEATURES GENERAL DESCRIPTION APPLICATIONS ORDERING INFORMATION QUICK REFERENCE DATA BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION VIF amplifier Tuner AGC and VIF-AGC VIF-AGC detector FPLL detector VCO and divider AFC and digital acquisition help Video demodulator and amplifier Sound carrier trap SIF amplifier SIF-AGC detector Single reference QSS mixer AM demodulator FM demodulator and acquisition help Audio amplifier and mute time constant Internal voltage stabilizer I2C-bus transceiver and module address I2C-BUS CONTROL Read format Slave address Data byte Write format Subaddress Data byte for switching mode Data byte for adjust mode Data byte for data mode 10 11 12 13 14 15 15.1 15.2 15.3 15.4 15.5 16 17 18 19
TDA9885; TDA9886
LIMITING VALUES THERMAL CHARACTERISTICS CHARACTERISTICS TEST AND APPLICATION INFORMATION PACKAGE OUTLINES SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS PURCHASE OF PHILIPS I2C COMPONENTS
2003 Oct 02
2
Philips Semiconductors
Product specification
I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
1 FEATURES
TDA9885; TDA9886
* 5 V supply voltage * Gain controlled wide-band Vision Intermediate Frequency (VIF) amplifier, AC-coupled * Multistandard true synchronous demodulation with active carrier regeneration: very linear demodulation, good intermodulation figures, reduced harmonics, and excellent pulse response * Gated phase detector for L and L-accent standard * Fully integrated VIF Voltage Controlled Oscillator (VCO), alignment-free, frequencies switchable for all negative and positive modulated standards via I2C-bus * Digital acquisition help, VIF frequencies of 33.4, 33.9, 38.0, 38.9, 45.75, and 58.75 MHz * 4 MHz reference frequency input: signal from Phase-Locked Loop (PLL) tuning system or operating as crystal oscillator * VIF Automatic Gain Control (AGC) detector for gain control, operating as peak sync detector for negative modulated signals and as a peak white detector for positive modulated signals * External AGC setting via pin OP1 * Precise fully digital Automatic Frequency Control (AFC) detector with 4-bit digital-to-analog converter, AFC bits readable via I2C-bus * TakeOver Point (TOP) adjustable via I2C-bus or alternatively with potentiometer * Fully integrated sound carrier trap for 4.5, 5.5, 6.0, and 6.5 MHz, controlled by FM-PLL oscillator * Sound IF (SIF) input for single reference Quasi Split Sound (QSS) mode, PLL controlled 4 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA9885T/V3 TDA9885TS/V3 TDA9885HN/V3 TDA9886T/V4 TDA9886TS/V4 TDA9886HN/V4 SO24 SSOP24 HVQFN32 SO24 SSOP24 HVQFN32 DESCRIPTION plastic small outline package; 24 leads; body width 7.5 mm plastic shrink small outline package; 24 leads; body width 5.3 mm plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm plastic small outline package; 24 leads; body width 7.5 mm plastic shrink small outline package; 24 leads; body width 5.3 mm plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm VERSION SOT137-1 SOT340-1 SOT617-3 SOT137-1 SOT340-1 SOT617-3 * SIF-AGC for gain controlled SIF amplifier, single reference QSS mixer able to operate in high performance single reference QSS mode and in intercarrier mode, switchable via I2C-bus * AM demodulator without extra reference circuit * Alignment-free selective FM-PLL demodulator with high linearity and low noise * Four selectable I2C-bus addresses * I2C-bus control for all functions * I2C-bus transceiver with pin programmable Module Address (MAD). 2 GENERAL DESCRIPTION
The TDA9885 is an alignment-free multistandard (PAL and NTSC) vision and sound IF signal PLL demodulator for negative modulation only and FM processing. The TDA9886 is an alignment-free multistandard (PAL, SECAM and NTSC) vision and sound IF signal PLL demodulator for positive and negative modulation, including sound AM and FM processing. 3 APPLICATIONS
* TV, VTR, PC, and STB applications.
2003 Oct 02
3
Philips Semiconductors
Product specification
I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
5 QUICK REFERENCE DATA SYMBOL VP IP Video part Vi(VIF)(rms) GVIF(cr) fVIF VIF input voltage sensitivity (RMS value) VIF gain control range -1 dB video at output see Fig.7 PARAMETER supply voltage supply current CONDITIONS notes 1 and 2
TDA9885; TDA9886
MIN. 4.5 52 - 60 - - - - - -
TYP. 5.0 63
MAX. 5.5 70
UNIT V mA V dB MHz MHz MHz MHz MHz MHz MHz
60 66 33.4 33.9 38.0 38.9 45.75 58.75 2.3
100 - - - - - - - -
vision carrier operating frequencies see Table 14
fVIF Vo(v)(p-p)
VIF frequency window of digital acquisition help video signal output voltage (peak-to-peak value)
related to fVIF; see Fig.10 see Fig.5 normal mode trap bypass mode
-
1.7 0.95 - - - 5
2.0 1.10 - - 2 6
2.3 1.25 5 7 4 -
V V % % deg MHz
Gdif
differential gain
"CCIR 330"; note 3
B/G standard L standard
dif Bv(-1dB) Bv(-3dB)(trap)
differential phase -1 dB video bandwidth -3 dB video bandwidth including sound carrier trap
"CCIR 330"
trap bypass mode; AC load; CL < 20 pF; RL > 1 k note 4 ftrap = 4.5 MHz ftrap = 5.5 MHz ftrap = 6.0 MHz ftrap = 6.5 MHz
3.95 4.90 5.40 5.50 30 30
4.05 5.00 5.50 5.95 36 36 59
- - - - - - -
MHz MHz MHz MHz dB dB dB
SC1 S/NW
trap attenuation at first sound carrier weighted signal-to-noise ratio
M/N standard B/G standard
weighted in accordance with 56 "CCIR 567"; see Fig.11; note 5 fripple = 70 Hz; video signal; grey level; positive and negative modulation; see Fig.6 definition: IAFC/fVIF 20
PSRRCVBS
power supply ripple rejection at pin CVBS
25
-
dB
AFCstps
AFC control steepness
0.85
1.05
1.25
A/kHz
2003 Oct 02
4
Philips Semiconductors
Product specification
I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
SYMBOL Audio part Vo(AF)(rms) THD AF output voltage (RMS value) total harmonic distortion of audio signal -3 dB AF bandwidth weighted signal-to-noise ratio of audio signal 27 kHz FM deviation; 50 s de-emphasis FM: 27 kHz FM deviation; 50 s de-emphasis AM: m = 54 % BAF(-3dB) S/NW(AF) without de-emphasis; dependent on FM-PLL filter FM: 27 kHz FM deviation; 50 s de-emphasis; vision carrier unmodulated AM: m = 54 % AM(sup) AM suppression of FM demodulator 50 s de-emphasis; AM: f = 1 kHz and m = 54 %; referenced to 27 kHz FM deviation fripple = 70 Hz; see Fig.6 for AM for FM Vo(intc)(rms) IF intercarrier output level (RMS value) QSS mode; SC1; SC2 off L standard; without modulation intercarrier mode; PC/SC1 = 20 dB; SC2 off; note 6 Reference frequency fref Vref(rms) Notes 1. Values of video and sound parameters can be decreased at VP = 4.5 V. reference signal frequency reference signal voltage (RMS value) note 7 operation as input terminal PARAMETER CONDITIONS
TDA9885; TDA9886
MIN.
TYP.
MAX.
UNIT
430 - - 80 52
540 0.15 0.5 100 56
650 0.50 1.0 - -
mV % % kHz dB
45 40
50 46
- -
dB dB
PSRRAUD
power supply ripple rejection on pin AUD
20 14 90 90 -
26 20 140 140 75
- - 180 180 -
dB dB mV mV mV
- 80
4 -
- 400
MHz mV
2. For applications without I2C-bus, the time constant (R x C) at the supply must be >1.2 s (e.g. 1 and 2.2 F). 3. Condition: luminance range (5 steps) from 0 % to 100 %. 4. AC load: CL < 20 pF and RL > 1 k. The sound carrier frequencies (depending on the TV standard) are attenuated by the integrated sound carrier traps (see Figs 13 to 18; H (s) is the absolute value of transfer function). 5. S/NW is the ratio of the black-to-white amplitude to the black level noise voltage (RMS value measured on pin CVBS). B = 5 MHz weighted in accordance with "CCIR 567".
2003 Oct 02
5
Philips Semiconductors
Product specification
I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
TDA9885; TDA9886
6. The intercarrier output signal at pin SIOMAD can be calculated by the following formula taking into account the internal video signal with 1.1 V (p-p) as a reference: 1 r V o(intc)(rms) = 1.1 x ---------- x 10 V 22 V i(SC) 1 and r = ----- x ------------- ( dB ) + 6 dB 3 dB - V i(PC) 20 where: V i ( SC ) 1 ---------- is the correction term for RMS value, --------------- ( dB ) is the sound-to-picture carrier ratio at pins VIF1 and VIF2 V i ( PC ) 22 in dB, 6 dB is the correction term of internal circuitry and 3 dB is the tolerance of video output and intercarrier output Vo(intc)(rms). 7. Pin REF is able to operate as a 1-pin crystal oscillator input as well as an external reference signal input, e.g. from the tuning system.
2003 Oct 02
6
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CVAGC(pos) VAGC (1) 16 (17) CBL RC VCO DIGITAL VCO CONTROL AFC DETECTOR VIF-PLL filter VPLL 19 (21) TOP 9 (8) TAGC 14 (15) CAGC(neg) TUNER AGC VIF-AGC VIF2 VIF1 2 (31) 1 (30) VIF-PLL
6
Philips Semiconductors
handbook, full pagewidth
I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
BLOCK DIAGRAM
external reference signal or 4 MHz crystal
REF 15 (16)
AFC 21 (23)
SOUND CARRIER TRAPS 4.5 to 6.5 MHz
(18) 17
CVBS video output: 2 V (p-p) [1.1 V (p-p) without trap]
TDA9885 TDA9886
(7) 8 SIF2 SIF1 24 (27) 23 (26) SINGLE REFERENCE QSS MIXER INTERCARRIER MIXER AND AM DEMODULATOR MAD (4) 6 SUPPLY SIF-AGC CAGC (6, 12, 13, 14, 17, 19, 25, 28, 29, 32) 13 n.c. OUTPUT PORTS I 2C-BUS TRANSCEIVER NARROW-BAND FM-PLL DEMODULATOR AUDIO PROCESSING AND SWITCHES (3) 5
AUD DEEM
7
20 (22) VP 18 (20) AGND
audio output
de-emphasis network AFD CAF
TDA9885; TDA9886
3 (1) OP1
22 (24) 11 (10) OP2 SCL
10 (9) SDA
7 (5) DGND
12 (11) SIOMAD
4 (2) FMPLL FM-PLL filter
MHC108
Product specification
sound intercarrier output and MAD select (1) Not connected for TDA9885. Pin numbers for TDA9885HN and TDA9886HN in parenthesis.
Fig.1 Block diagram.
Philips Semiconductors
Product specification
I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
7 PINNING PIN SYMBOL VIF1 VIF2 n.c. OP1 FMPLL DEEM AFD DGND n.c. AUD TOP SDA SCL SIOMAD n.c. n.c. n.c. TAGC REF VAGC n.c. CVBS n.c. AGND VPLL VP AFC OP2 n.c. SIF1 SIF2 n.c. n.c. TDA9885T TDA9886T TDA9885HN TDA9886HN TDA9885TS TDA9886TS 1 2 - 3 4 5 6 7 - 8 9 10 11 12 - 13 - 14 15 - 16 17 - 18 19 20 21 22 - 23 24 - - 1 2 - 3 4 5 6 7 - 8 9 10 11 12 - 13 - 14 15 16 - 17 - 18 19 20 21 22 - 23 24 - - 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 - 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 - 18 19 20 21 22 23 24 25 26 27 28 29
TDA9885; TDA9886
DESCRIPTION VIF differential input 1 VIF differential input 2 not connected output port 1; open-collector FM-PLL for loop filter de-emphasis output for capacitor AF decoupling input for capacitor digital ground not connected audio output tuner AGC TakeOver Point (TOP) for resistor adjustment I2C-bus data input and output I2C-bus clock input sound intercarrier output and MAD select with resistor not connected not connected not connected tuner AGC output 4 MHz crystal or reference signal input VIF-AGC for capacitor not connected composite video output not connected analog ground VIF-PLL for loop filter supply voltage AFC output output port 2; open-collector not connected SIF differential input 1 and MAD select with resistor SIF differential input 2 and MAD select with resistor not connected not connected
2003 Oct 02
8
Philips Semiconductors
Product specification
I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
TDA9885; TDA9886
handbook, halfpage
handbook, halfpage
VIF1 1 VIF2 2 OP1 3 FMPLL 4 DEEM 5 AFD 6 DGND 7 AUD 8 TOP 9 SDA 10 SCL 11 SIOMAD 12
MHC109
24 SIF2 23 SIF1 22 OP2 21 AFC 20 VP 19 VPLL TDA9885T TDA9886T 18 AGND 17 CVBS 16 VAGC (1) 15 REF 14 TAGC 13 n.c.
VIF1 1 VIF2 2 OP1 3 FMPLL 4 DEEM 5 AFD 6 DGND 7 AUD 8 TOP 9 SDA 10 SCL 11 SIOMAD 12
MHC110
24 SIF2 23 SIF1 22 OP2 21 AFC 20 VP 19 VPLL TDA9885TS TDA9886TS 18 AGND 17 CVBS 16 VAGC (1) 15 REF 14 TAGC 13 n.c.
(1) Not connected for TDA9885T.
(1) Not connected for TDA9885TS.
Fig.2 Pin configuration for SO24.
Fig.3 Pin configuration for SSOP24.
11 SIOMAD
15 TAGC
SDA
9
handbook, halfpage
16 REF
10 SCL
12 n.c.
13 n.c.
14 n.c.
TOP AUD n.c. DGND AFD DEEM FMPLL OP1
8 7 6 5 4 3 2 1
n.c. 32 VIF2 31 VIF1 30 n.c. 29 n.c. 28 SIF2 27 SIF1 26 n.c. 25
17 VAGC(1) 18 CVBS 19 n.c. 20 AGND 21 VPLL 22 VP 23 AFC 24 OP2
TDA9885HN TDA9886HN
terminal 1 index area
MHC111
Bottom view. (1) Not connected for TDA9885HN.
Fig.4 Pin configuration for HVQFN32.
2003 Oct 02
9
Philips Semiconductors
Product specification
I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
8 FUNCTIONAL DESCRIPTION 8.3
TDA9885; TDA9886
VIF-AGC detector
Figure 1 shows the simplified block diagram of the device which comprises the following functional blocks: * VIF amplifier * Tuner AGC and VIF-AGC * VIF-AGC detector * Frequency Phase-Locked Loop (FPLL) detector * VCO and divider * AFC and digital acquisition help * Video demodulator and amplifier * Sound carrier trap * SIF amplifier * SIF-AGC detector * Single reference QSS mixer * AM demodulator * FM demodulator and acquisition help * Audio amplifier and mute time constant * Internal voltage stabilizer * I2C-bus transceiver and MAD (module address). 8.1 VIF amplifier
Gain control is performed by sync level detection (negative modulation) or peak white detection (positive modulation). For negative modulation, the sync level voltage is stored at an integrated capacitor by means of a fast peak detector. This voltage is compared with a reference voltage (nominal sync level) by a comparator which charges or discharges the integrated AGC capacitor for the generation of the required VIF gain. The time constants for decreasing or increasing the gain are nearly equal and the total AGC reaction time is fast to cope with `aeroplane fluttering'. For positive modulation, the white peak level voltage is compared with a reference voltage (nominal white level) by a comparator which charges (fast) or discharges (slow) the external AGC capacitor directly for the generation of the required VIF gain. The need of a very long time constant for VIF gain increase is because the peak white level may appear only once in a field. In order to reduce this time constant, an additional level detector increases the discharging current of the AGC capacitor (fast mode) in the event of a decreasing VIF amplitude step controlled by the detected actual black level voltage. The threshold level for fast mode AGC is typically -6 dB video amplitude. The fast mode state is also transferred to the SIF-AGC detector for speed-up. In case of missing peak white pulses, the VIF gain increase is limited to typically +3 dB by comparing the detected actual black level voltage with a corresponding reference voltage. 8.4 FPLL detector
The VIF amplifier consists of three AC-coupled differential stages. Gain control is performed by emitter degeneration. The total gain control range is typically 66 dB. The differential input impedance is typically 2 k in parallel with 3 pF. 8.2 Tuner AGC and VIF-AGC
This block adapts the voltages, generated at the VIF-AGC and SIF-AGC detectors, to the internal signal processing at the VIF and SIF amplifiers and performs the tuner AGC control current generation. The onset of the tuner AGC control current generation can be set either via the I2C-bus (see Table 13) or optionally by a potentiometer at pin TOP (in case that the I2C-bus information cannot be stored, related to the device). The presence of a potentiometer is automatically detected and the I2C-bus setting is disabled. Furthermore, derived from the AGC detector voltage, a comparator is used to test if the corresponding VIF input voltage is higher than 200 V. This information can be read out via the I2C-bus (bit VIFLEV = 1).
The VIF amplifier output signal is fed into a frequency detector and into a phase detector via a limiting amplifier for removing the video AM. During acquisition the frequency detector produces a current proportional to the frequency difference between the VIF and the VCO signals. After frequency lock-in the phase detector produces a current proportional to the phase difference between the VIF and the VCO signals. The currents from the frequency and phase detectors are charged into the loop filter which controls the VIF VCO and locks it to the frequency and phase of the VIF carrier. For a positive modulated VIF signal, the charging currents are gated by the composite sync in order to avoid signal distortion in case of overmodulation. The gating depth is switchable via the I2C-bus.
2003 Oct 02
10
Philips Semiconductors
Product specification
I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
8.5 VCO and divider 8.7
TDA9885; TDA9886
Video demodulator and amplifier
The VCO of the VIF-FPLL operates as an integrated low radiation relaxation oscillator at double the picture carrier frequency. The control voltage, required to tune the VCO to double the picture carrier frequency, is generated at the loop filter by the frequency phase detector. The possible frequency range is 50 to 140 MHz (typical value). The oscillator frequency is divided-by-two to provide two differential square wave signals with exactly 90 degrees phase difference, independent of the frequency, for use in the FPLL detectors, the video demodulator and the intercarrier mixer. 8.6 AFC and digital acquisition help
The video demodulator is realized by a multiplier which is designed for low distortion and large bandwidth. The VIF signal is multiplied with the `in phase' signal of the VIF-PLL VCO. The demodulator output signal is fed into the video preamplifier via a level shift stage with integrated low-pass filter to achieve carrier harmonics attenuation. The output signal of the preamplifier is fed to the VIF-AGC detector (see Section 8.3) and in the sound trap mode also fed internally to the integrated sound carrier trap (see Section 8.8). The differential trap output signal is converted and amplified by the following postamplifier. The video output level at pin CVBS is 2 V (p-p). In the bypass mode the output signal of the preamplifier is fed directly through the postamplifier to pin CVBS. The output video level is 1.1 V (p-p) for using an external sound trap with 10 % overall loss. Noise clipping is provided in both cases. 8.8 Sound carrier trap
Each relaxation oscillator of the VIF-PLL and FM-PLL demodulator has a wide frequency range. To prevent false locking of the PLLs and with respect to the catching range, the digital acquisition help provides an individual control, until the frequency of the VCO is within the preselected standard dependent lock-in window of the PLL. The in-window and out-window control at the FM-PLL is additionally used to mute the audio stage (if auto mute is selected via the I2C-bus). The working principle of the digital acquisition help is as follows. The PLL VCO output is connected to a down counter which has a predefined start value (standard dependent). The VCO frequency clocks the down counter for a fixed gate time. Thereafter, the down counter stop value is analysed. In case the stop value is higher (lower) than the expected value range, the VCO frequency is lower (higher) than the wanted lock-in window frequency range. A positive (negative) control current is injected into the PLL loop filter and consequently the VCO frequency is increased (decreased) and a new counting cycle starts. The gate time as well as the control logic of the acquisition help circuit is dependent on the precision of the reference signal at pin REF. Operation as a crystal oscillator is possible as well as connecting this input via a serial capacitor to an external reference frequency, e.g. the tuning system oscillator. The AFC signal is derived from the corresponding down counter stop value after a counting cycle. The last four bits are latched and can be read out via the I2C-bus (see Table 7). Also the digital-to-analog converted value is given as current at pin AFC.
The sound carrier trap consists of a reference filter, a phase detector and the sound trap itself. A sound carrier reference signal is fed into the reference low-pass filter and is shifted by nominal 90 degrees. The phase detector compares the original reference signal with the signal shifted by the reference filter and produces a DC voltage by charging or discharging an integrated capacitor with a current proportional to the phase difference between both signals, respectively to the frequency error of the integrated filters. The DC voltage controls the frequency position of the reference filter and the sound trap. So the accurate frequency position for the different standards is set by the sound carrier reference signal. The sound trap itself is constructed of three separate traps to realize sufficient suppression of the first and second sound carriers. 8.9 SIF amplifier
The SIF amplifier consists of three AC-coupled differential stages. Gain control is performed by emitter degeneration. The total gain control range is typically 66 dB. The differential input impedance is typically 2 k in parallel with 3 pF.
2003 Oct 02
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Philips Semiconductors
Product specification
I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
8.10 SIF-AGC detector 8.12
TDA9885; TDA9886
AM demodulator
SIF gain control is performed by the detection of the DC component of the AM demodulator output signal. This DC signal corresponds directly to the SIF voltage at the output of the SIF amplifier so that a constant SIF signal is supplied to the AM demodulator and to the single reference QSS mixer. By switching the gain of the input amplifier of the SIF-AGC detector via the I2C-bus, the internal SIF level for FM sound is 5.5 dB lower than for AM sound. This is to adapt the SIF-AGC characteristic to the VIF-AGC characteristic. The adaption is ideal for a picture-to-sound FM carrier ratio of 13 dB. Via a comparator, the integrated AGC capacitor is charged or discharged for the generation of the required SIF gain. Due to AM sound, the AGC reaction time is slow (fc < 20 Hz for the closed AGC loop). For reducing this AM sound time constant in the event of a decreasing IF amplitude step, the load current of the AGC capacitor is increased (fast mode) when the VIF-AGC detector (at positive modulation mode) operates in the fast mode too. An additional circuit (threshold approximately 7 dB) ensures a very fast gain reduction for a large increasing IF amplitude step. 8.11 Single reference QSS mixer
The amplitude modulated SIF amplifier output signal is fed both to a two-stage limiting amplifier that removes the AM and to a linear multiplier. The result of the multiplication of the SIF signal with the limiter output signal is AM demodulation (passive synchronous demodulator). The demodulator output signal is fed via a low-pass filter that attenuates the carrier harmonics and via the input amplifier of the SIF-AGC detector to the audio amplifier. 8.13 FM demodulator and acquisition help
The narrow-band FM-PLL detector consists of: * Gain controlled FM amplifier and AGC detector * Narrow-band PLL. The intercarrier signal from the intercarrier mixer is fed to the input of an AC-coupled gain controlled amplifier with two stages. The gain controlled output signal is fed to the phase detector of the narrow-band FM-PLL (FM demodulator). For good selectivity and robustness against disturbance caused by the video signal, a high linearity of the gain controlled FM amplifier and of the phase detector as well as a constant signal level are required. The gain control is done by means of an `in phase' demodulator for the FM carrier (from the output of the FM amplifier). The demodulation output is fed into a comparator for charging or discharging the integrated AGC capacitor. This leads to a mean value AGC loop to control the gain of the FM amplifier. The FM demodulator is realized as a narrow-band PLL with an external loop filter, which provides the necessary selectivity (bandwidth approximately 100 kHz). To achieve good selectivity, a linear phase detector and a constant input level are required. The gain controlled intercarrier signal from the FM amplifier is fed to the phase detector. The phase detector controls via the loop filter the integrated low radiation relaxation oscillator. The designed frequency range is from 4 to 7 MHz. The VCO within the FM-PLL is phase-locked to the incoming 2nd SIF signal, which is frequency modulated. As well as this, the VCO control voltage is superimposed by the AF voltage. Therefore, the VCO tracks with the FM of the 2nd SIF signal. So, the AF voltage is present at the loop filter and is typically 5 mV (RMS) for 27 kHz FM deviation. This AF signal is fed via a buffer to the audio amplifier. The correct locking of the PLL is supported by the digital acquisition help circuit (see Section 8.6).
With the present system a high performance Hi-Fi stereo sound processing can be achieved. For a simplified application without a SIF SAW filter, the single reference QSS mixer can be switched to the intercarrier mode via the I2C-bus. The single reference QSS mixer generates the 2nd FM TV sound intercarrier signal. It is realized by a linear multiplier which multiplies the SIF amplifier output signal and the VIF-PLL VCO signal (90 degrees output) which is locked to the picture carrier. In this way the QSS mixer operates as a quadrature mixer in the intercarrier mode and provides suppression of the low frequency video signals. The QSS mixer output signal is fed internally via a high-pass and low-pass combination to the FM demodulator as well as via an operational amplifier to the intercarrier output pin SIOMAD.
2003 Oct 02
12
Philips Semiconductors
Product specification
I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
8.14 Audio amplifier and mute time constant 8.15
TDA9885; TDA9886
Internal voltage stabilizer
The audio amplifier consists of two parts: * AF preamplifier * AF output amplifier. The AF preamplifier used for FM sound is an operational amplifier with internal feedback, high gain and high common mode rejection. The AF voltage from the PLL demodulator is 5 mV (RMS) for a frequency deviation of 27 kHz and is amplified by 30 dB. By the use of a DC operating point control circuit (with external capacitor CAF), the AF preamplifier is decoupled from the PLL DC voltage. The low-pass characteristic of the amplifier reduces the harmonics of the sound intercarrier signal at the AF output terminal. For FM sound a switchable de-emphasis network (with external capacitor) is implemented between the preamplifier and the output amplifier. The AF output amplifier provides the required AF output level by a rail-to-rail output stage. A preceding stage makes use of an input selector for switching between FM sound, AM sound and mute state. The gain can be switched between 10 dB (normal) and 4 dB (reduced). Switching to the mute state is controlled automatically, dependent on the digital acquisition help in case the VCO of the FM-PLL is not in the required frequency window. This is done by a time constant: fast for switching to the mute state and slow (typically 40 ms) for switching to the no-mute state. All switching functions are controlled via the I2C-bus: * AM sound, FM sound and forced mute * Auto mute enable or disable * De-emphasis off or on with 50 or 75 s * Audio gain normal or reduced.
The band gap circuit internally generates a voltage of approximately 2.4 V, independent of supply voltage and temperature. A voltage regulator circuit, connected to this voltage, produces a constant voltage of 3.55 V which is used as an internal reference voltage. 8.16 I2C-bus transceiver and module address
The device can be controlled via the 2-wire I2C-bus by a microcontroller. Two wires carry serial data (SDA) and serial clock (SCL) information between the devices connected to the I2C-bus. The device has an I2C-bus slave transceiver with auto-increment. The circuit operates up to clock frequencies of 400 kHz. A slave address is sent from the master to the slave receiver. To avoid conflicts in a real application with other devices providing similar or complementing functions, there are four possible slave addresses available. These Module Addresses (MADs) can be selected by connecting resistors on pin SIOMAD and/or pins SIF1 and SIF2 (see Fig.23). Pin SIOMAD relates with bit A0 and pins SIF1 and SIF2 relate with bit A3. The slave addresses of this device are given in Table 1. The power-on preset value is dependent on the use of pin SIOMAD and can be chosen for 45.75 MHz NTSC as default (pin SIOMAD left open-circuit) or 58.75 MHz NTSC (resistor on pin SIOMAD). In this way the device can be used without the I2C-bus as an NTSC only device. Remark: In case of using the device without the I2C-bus, then the rise time of the supply voltage after switching on power must be longer than 1.2 s.
2003 Oct 02
13
Philips Semiconductors
Product specification
I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
Table 1 Slave address detection SELECTABLE ADDRESS BIT SLAVE ADDRESS A3 MAD1 MAD2 MAD3 MAD4 9 9.1 I2C-BUS CONTROL Read format I2C-bus read format (slave transmits data) BYTE 1 A6 A5 A4 A3 A2 A1 A0 R/W 1 slave address Table 3 Explanation of Table 2 FUNCTION START condition, generated by the master see Table 4 read command, generated by the master acknowledge bit, generated by the slave 8-bit data word, transmitted by the slave (see Table 5) acknowledge-not bit, generated by the master STOP condition, generated by the master A D7 D6 D5 0 0 1 1 A0 1 0 1 0
TDA9885; TDA9886
RESISTOR ON PIN SIF1 AND SIF2 no no yes yes SIOMAD no yes no yes
Table 2 S
BYTE 2 D4 D3 D2 D1 D0 data
AN
P
SYMBOL S Slave address R/W = 1 A Data AN P
The master generates an acknowledge when it has received the dataword READ. The master next generates an acknowledge, then slave begins transmitting the dataword READ, and so on until the master generates an acknowledge-not bit and transmits a STOP condition.
2003 Oct 02
14
Philips Semiconductors
Product specification
I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
9.1.1 SLAVE ADDRESS
TDA9885; TDA9886
The first module address MAD1 is the standard address (see Table 1). Table 4 Slave addresses; notes 1 and 2 BIT A6 1 1 1 1 A5 0 0 0 0 A4 0 0 0 0 A3 0 0 1 1 A2 0 0 0 0 A1 1 1 1 1 A0 1 0 1 0
SLAVE ADDRESS NAME MAD1 MAD2 MAD3 MAD4 Notes 1. For MAD activation via external resistor: see Table 1 and Fig.23. 2. For applications without I2C-bus: see Tables 17 and 18. 9.1.2 Table 5 MSB D7 AFCWIN Table 6 BIT AFCWIN 1 0 VIFLEV 1 0 CARRDET 1 0 AFC[4:1] PONR 1 0 Note D6 VIFLEV D5 CARRDET D4 AFC4 D3 AFC3 DATA BYTE Data read register (status register) VALUE (HEX) 43 42 4B 4A
LSB D2 AFC2 D1 AFC1 D0 PONR
Description of status register bits VALUE AFC window VCO in 1.6 MHz AFC window; note 1 VCO out of 1.6 MHz AFC window VIF input level high level; VIF input voltage 200 V (typically) low level FM carrier detection detection no detection Automatic frequency control see Table 7 Power-on reset after Power-on reset or after supply breakdown after a successful reading of the status register DESCRIPTION
1. If no IF input is applied, then bit AFCWIN = 1 due to the fact that the VCO is forced to the AFC window border for fast lock-in behaviour.
2003 Oct 02
15
Philips Semiconductors
Product specification
I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
Table 7 Automatic frequency control bits; note 1 BIT AFC4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Note 1. f0 is the nominal frequency of fVIF. 9.2 Write format I2C-bus write format (slave receives data); note 1 BYTE 1 A6 to A0 slave address Note 1. The auto-increment of the subaddress stops if the subaddress is 3. Table 9 Explanation of Table 8 SYMBOL S Slave address R/W = 0 A Subaddress (SAD) Data 1, data n P see Table 4 write command, generated by the master acknowledge bit, generated by the slave see Table 10 FUNCTION START condition, generated by the master R/W 0 A BYTE 2 A7 to A0 subaddress A BYTE 3 bits 7 to 0 data 1 AFC3 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 AFC2 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 AFC1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
TDA9885; TDA9886
fVIF (f0 - 187.5 kHz) f0 - 162.5 kHz f0 - 137.5 kHz f0 - 112.5 kHz f0 - 87.5 kHz f0 - 62.5 kHz f0 - 37.5 kHz f0 - 12.5 kHz f0 + 12.5 kHz f0 + 37.5 kHz f0 + 62.5 kHz f0 + 87.5 kHz f0 + 112.5 kHz f0 + 137.5 kHz f0 + 162.5 kHz (f0 + 187.5 kHz)
Table 8 S
A
BYTE n bits 7 to 0 data n
A
P
8-bit data words, transmitted by the master (see Tables 11, 12 and 14) STOP condition
2003 Oct 02
16
Philips Semiconductors
Product specification
I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
9.2.1 SUBADDRESS
TDA9885; TDA9886
If more than one data byte is transmitted, then auto-increment is performed: starting from the transmitted subaddress and auto-increment of subaddress in accordance with the order of Table 10. Table 10 Definition of the subaddress (second byte after slave address); note 1 MSB REGISTER SAD for switching mode SAD for adjust mode SAD for data mode Notes 1. X = don't care. 2. Bit A7 = 1 is not allowed. 3. Bits A6 to A2 will be ignored by the internal hardware. 9.2.2 DATA BYTE FOR SWITCHING MODE A7(2) 0 0 0 A6(3) X X X A5(3) X X X A4(3) X X X A3(3) X X X A2(3) X X X A1 0 0 1 LSB A0 0 1 0
Table 11 Bit description of SAD register for switching mode (SAD = 00) BIT B7 1 0 B6 1 0 B5 1 0 B4 and B3 00 01 10 11 B2 1 0 B1 1 0 VALUE high-impedance, disabled or HIGH low-impedance, active or LOW Output port 1 for SAW switching or external input high-impedance, disabled or HIGH low-impedance, active or LOW Forced audio mute on off TV standard modulation positive AM TV; note 1 not used negative FM TV not used Carrier mode QSS mode intercarrier mode Auto mute of FM AF output active inactive DESCRIPTION Output port 2 for SAW switching or monitoring
2003 Oct 02
17
Philips Semiconductors
Product specification
I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
BIT B0 1 0 Note 1. For positive AM TV choose 6.5 MHz for the second SIF. 9.2.3 DATA BYTE FOR ADJUST MODE VALUE Video mode (sound trap) sound trap bypass sound trap active DESCRIPTION
TDA9885; TDA9886
Table 12 Bit description of SAD register for adjust mode (SAD = 01) BIT C7 1 0 C6 1 0 C5 1 0 C4 to C0 VALUE Audio gain -6 dB 0 dB De-emphasis time constant 50 s 75 s De-emphasis on off Tuner takeover point adjustment see Table 13 DESCRIPTION
2003 Oct 02
18
Philips Semiconductors
Product specification
I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
Table 13 Tuner takeover point adjustment bits BIT
TDA9885; TDA9886
TOP ADJUSTMENT (dB) C4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note 1. 0 dB is equal to 17 mV (RMS). C3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 C2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 C1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 C0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0(1) -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 -16
2003 Oct 02
19
Philips Semiconductors
Product specification
I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
9.2.4 DATA BYTE FOR DATA MODE
TDA9885; TDA9886
Table 14 Bit description of SAD register for data mode (SAD = 10) BIT E7 E6 1 0 E5 E4 to E2 E1 and E0 00 01 10 11 Note 1. For positive modulation choose 6.5 MHz. Table 15 Options in extended TV mode; bit B3 = 0 of SAD 00 register BIT E7 = 0 FUNCTION BIT E5 = 0 Pin OP1 Pin OP2 Gain Note 1. The corresponding port function has to be disabled (set to `high-impedance'); see Table 11 and Chapter 12, Table of Characteristics, note 12. port function port function normal gain BIT E5 = 1 port function port function minimum gain BIT E5 = 0 port function VIF-AGC output(1) normal gain BIT E5 = 1 VIF-AGC external input(1) port function external gain BIT E7 = 1 VALUE VIF-AGC and port features dependent on bit E5; see Table 15 L standard PLL gating gating in case of 36 % positive modulation gating in case of 0 % positive modulation VIF, SIF and tuner minimum gain dependent on bit E7; see Table 15 Vision intermediate frequency selection see Table 16 Sound intercarrier frequency selection (sound 2nd IF) fFM = 4.5 MHz fFM = 5.5 MHz fFM = 6.0 MHz fFM = 6.5 MHz; note 1 DESCRIPTION
2003 Oct 02
20
Philips Semiconductors
Product specification
I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
Table 16 TV standard selection for VIF VIDEO IF SELECT BITS E4 0 0 0 0 1 1 1 1 Note E3 0 0 1 1 0 0 1 1 E2 0 1 0 1 0 1 0 1
TDA9885; TDA9886
fVIF (MHz) 58.75(1) 45.75(1) 38.9 38.0 33.9 33.4 not applicable not applicable
1. Pin SIOMAD can be used for the selection of the different NTSC standards without I2C-bus. With a resistor on pin SIOMAD, fVIF = 58.75 MHz; without a resistor on pin SIOMAD, fVIF = 45.75 MHz (NTSC-M). Table 17 Data setting after power-on reset (default setting with a resistor on pin SIOMAD) MSB REGISTER D7 Switching mode Adjust mode Data mode 1 0 0 D6 1 0 0 D5 0 1 0 D4 1 1 0 D3 0 0 0 D2 1 0 0 D1 1 0 0 D0 0 0 0 LSB
Table 18 Data setting after power-on reset (default setting without a resistor on pin SIOMAD) MSB REGISTER D7 Switching mode Adjust mode Data mode 1 0 0 D6 1 0 0 D5 0 1 0 D4 1 1 0 D3 0 0 0 D2 1 0 1 D1 1 0 0 D0 0 0 0 LSB
2003 Oct 02
21
Philips Semiconductors
Product specification
I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
10 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VP Vn supply voltage voltage on pins VIF1, VIF2, SIF1, SIF2, OP1, OP2, VP, and FMPLL pin TAGC tsc Tstg Tamb short-circuit time to ground or VP storage temperature ambient temperature TDA9885T (SO24), TDA9885TS (SSOP24), TDA9886T (SO24) and TDA9886TS (SSOP24) TDA9885HN (HVQFN32) and TDA9886HN (HVQFN32) Ves electrostatic discharge voltage on all pins note 1 note 2 Notes PARAMETER
TDA9885; TDA9886
CONDITIONS - 0 0 -
MIN.
MAX. 5.5 VP 8.8 10 +150 +70 +85 +400 +3500 V V V s
UNIT
-25 -20 -20 -400 -4000
C C C V V
1. Machine model in accordance with SNW-FQ-302B: class C, discharging a 200 pF capacitor via a 0.75 H series inductance. 2. Human body model in accordance with SNW-FQ-302A: class 2, discharging a 100 pF capacitor via a 1.5 k series resistor. 11 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) TDA9885T (SO24) TDA9885TS (SSOP24) TDA9885HN (HVQFN32) TDA9886T (SO24) TDA9886TS (SSOP24) TDA9886HN (HVQFN32) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air 76 118 40 76 118 40 K/W K/W K/W K/W K/W K/W VALUE UNIT
2003 Oct 02
22
Philips Semiconductors
Product specification
I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
TDA9885; TDA9886
12 CHARACTERISTICS VP = 5 V; Tamb = 25 C; see Table 20 for input frequencies; B/G standard is used for the specification (fPC = 38.9 MHz; fSC = 33.4 MHz; PC/SC = 13 dB; fmod = 400 Hz); input level Vi(VIF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation DSB; residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "CCIR line 17 and line 330" or "NTC-7 Composite"; measurements taken in test circuit of Fig.23; unless otherwise specified. SYMBOL Supply (pin VP) VP IP Ptot POWER-ON RESET VP(start) VP(stop) supply voltage for start of reset supply voltage for end of reset decreasing supply voltage increasing supply voltage; I2C-bus transmission enable for applications without I2C-bus -1 dB video at output +1 dB video at output note 2 within AGC range; f = 5.5 MHz see Fig.7 2.5 - 3.0 - 3.5 4.4 V V supply voltage supply current total power dissipation note 1 4.5 52 - 5.0 63 305 5.5 70 385 V mA mW PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
P
time constant (R x C) for network at pin VP VIF input voltage sensitivity (RMS value) maximum input voltage (RMS value) overload input voltage (RMS value) internal IF amplitude difference between picture and sound carrier VIF gain control range lower limit -3 dB VIF bandwidth upper limit -3 dB VIF bandwidth differential input resistance differential input capacitance DC input voltage
1.2
-
-
s
VIF amplifier (pins VIF1 and VIF2) Vi(VIF)(rms) Vi(max)(rms) Vi(ovl)(rms) VIF(int) - 150 - - 60 190 - 0.7 100 - 440 - V mV mV dB
GVIF(cr) BVIF(-3dB)(ll) BVIF(-3dB)(ul) Ri(dif) Ci(dif) VI fVCO(max) fVIF
60 - -
66 15 80 2 3 1.93
- - - - - - - - - - - - -
dB MHz MHz k pF V
note 3 note 3
- - -
FPLL and true synchronous video demodulator; note 4 maximum oscillator frequency for carrier regeneration vision carrier operating frequencies f = 2fPC see Table 14 120 - - - - - - 2003 Oct 02 23 140 33.4 33.9 38.0 38.9 45.75 58.75 MHz MHz MHz MHz MHz MHz MHz
Philips Semiconductors
Product specification
I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
SYMBOL fVIF tacq Vi(lock)(rms) PARAMETER VIF frequency window of digital acquisition help acquisition time input voltage sensitivity for PLL to be locked (RMS value) cycle time of digital acquisition help VIF VCO steepness VIF phase detector steepness definition: fVIF/VVPLL definition: IVPLL/VIF CONDITIONS related to fVIF; see Fig.10 BL = 70 kHz; note 5 - - MIN.
TDA9885; TDA9886
TYP. 2.3 - 30 -
MAX.
UNIT MHz ms V
30 70
measured on pins VIF1 - and VIF2; maximum IF gain - - -
Tcy(DAH) KO(VIF) KD(VIF)
64 20 23
- - -
s MHz/V A/rad
Video output 2 V (pin CVBS) NORMAL MODE (SOUND CARRIER TRAP ACTIVE) AND SOUND CARRIER ON Vo(v)(p-p) Vo V/S Vsync Vclip(u) Vclip(l) Ro Ibias(int) Io(sink)(max) Io(source)(max) Vo(CVBS) Vo(bl) Vo(bl)(v) video output voltage (peak-to-peak value) video output voltage difference ratio between video (black-to-white) and sync level sync voltage level upper video clipping voltage level lower video clipping voltage level output resistance internal DC bias current for emitter-follower maximum AC and DC output sink current maximum AC and DC output source current deviation of CVBS output voltage black level tilt vertical black level tilt for worst case in L standard differential gain 50 dB gain control 30 dB gain control negative modulation vision carrier modulated by test line (VITS) only note 3 see Fig.5 difference between L and B/G standard 1.7 -12 1.90 1.0 2.0 - 2.33 1.2 2.3 +12 3.00 1.4 - 0.9 30 - - - 0.5 0.1 1 3 V V V mA mA mA dB dB % % V %
VP - 1.1 VP - 1 - - 1.5 1 3.9 - - - - 0.7 - 2.0 - - - - - -
Gdif
"CCIR 330"; note 6
B/G standard L standard - - - - - 2 59 5 7 4 - % % deg dB
dif S/NW
differential phase weighted signal-to-noise ratio
"CCIR 330"
weighted in accordance 56 with "CCIR 567"; see Fig.11; note 7
2003 Oct 02
24
Philips Semiconductors
Product specification
I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
SYMBOL S/NUW IM(blue) PARAMETER intermodulation attenuation at `blue' CONDITIONS see Fig.12; note 8 f = 1.1 MHz f = 3.3 MHz IM(yellow) intermodulation attenuation at `yellow' see Fig.12; note 8 f = 1.1 MHz f = 3.3 MHz Vr(PC)(rms) funw(p-p) residual picture carrier (RMS value) robustness for unwanted frequency deviation of picture carrier (peak-to-peak value) robustness for modulator imbalance fundamental wave and harmonics 3 % residual carrier; 50 % serration pulses; L standard; note 3 0 % residual carrier; 50 % serration pulses; L standard; L-gating = 0 %; note 3 CL < 20 pF; RL > 1 k; AC load; note 9a note 9b 60 59 - - 58 58 MIN. 47
TDA9885; TDA9886
TYP. 51 64 64 66 65 2 - - - - - - 5
MAX.
UNIT dB dB dB dB dB mV kHz
unweighted signal-to-noise ratio note 7
12
-
-
3
%
H spur PSRRCVBS
suppression of video signal harmonics suppression of spurious elements power supply ripple rejection at pin CVBS
35 40
40 - 25
- - -
dB dB dB
fripple = 70 Hz; 20 video signal; grey level; positive and negative modulation; see Fig.6
M/N STANDARD INCLUDING KOREA; see Fig 13 Bv(-3dB)(trap) SC1 SC1(60kHz) SC2 SC2(60kHz) td(g)(cc) -3 dB video bandwidth including sound carrier trap attenuation at first sound carrier fSC1 60 kHz attenuation at second sound carrier attenuation at second sound carrier fSC2 60 kHz group delay at colour carrier frequency -3 dB video bandwidth including sound carrier trap attenuation at first sound carrier fSC1 60 kHz attenuation at second sound carrier ftrap = 4.5 MHz; note 10 3.95 30 21 21 15 110 4.05 36 27 27 21 180 - - - - - 250 MHz dB dB dB dB ns
attenuation at first sound carrier f = 4.5 MHz f = 4.5 MHz f = 4.724 MHz f = 4.724 MHz f = 3.58 MHz; see Fig.14
B/G STANDARD; see Fig.15 Bv(-3dB)(trap) SC1 SC1(60kHz) SC2 ftrap = 5.5 MHz; note 10 4.90 30 24 21 5.00 36 30 27 - - - - MHz dB dB dB
attenuation at first sound carrier f = 5.5 MHz f = 5.5 MHz f = 5.742 MHz
2003 Oct 02
25
Philips Semiconductors
Product specification
I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
SYMBOL SC2(60kHz) td(g)(cc) PARAMETER attenuation at second sound carrier fSC2 60 kHz group delay at colour carrier frequency -3 dB video bandwidth including sound carrier trap attenuation at first sound carrier fSC1 60 kHz attenuation at second sound carrier attenuation at second sound carrier fSC2 60 kHz group delay at colour carrier frequency -3 dB video bandwidth including sound carrier trap attenuation at first sound carrier fSC1 60 kHz attenuation at second sound carrier attenuation at second sound carrier fSC2 60 kHz group delay at colour carrier frequency CONDITIONS f = 5.742 MHz f = 4.43 MHz; see Fig.16 MIN. 15 110
TDA9885; TDA9886
TYP. 21 180 -
MAX.
UNIT dB ns
250
I STANDARD; see Fig.17 Bv(-3dB)(trap) SC1 SC1(60kHz) SC2 SC2(60kHz) td(g)(cc) ftrap = 6.0 MHz; note 10 5.40 26 20 12 10 - 5.50 32 26 18 15 90 - - - - - 160 MHz dB dB dB dB ns
attenuation at first sound carrier f = 6.0 MHz f = 6.0 MHz f = 6.55 MHz f = 6.55 MHz f = 4.43 MHz
D/K STANDARD; see Fig.18 Bv(-3dB)(trap) SC1 SC1(60kHz) SC2 SC2(60kHz) td(g)(cc) ftrap = 6.5 MHz; note 10 5.50 26 20 18 13 - 5.95 32 26 24 18 60 - - - - - 130 MHz dB dB dB dB ns
attenuation at first sound carrier f = 6.5 MHz f = 6.5 MHz f = 6.742 MHz f = 6.742 MHz f = 4.28 MHz
Video output 1.1 V (pin CVBS) TRAP BYPASS MODE AND SOUND CARRIER OFF; note 11 Vo(v)(p-p) Vsync Vclip(u) Vclip(l) Bv(-1dB) Bv(-3dB) video output voltage (peak-to-peak value) sync voltage level upper video clipping voltage level lower video clipping voltage level -1 dB video bandwidth -3 dB video bandwidth CL < 20 pF; RL > 1 k; AC load CL < 20 pF; RL > 1 k; AC load see Fig.5 0.95 1.35 3.5 - 5 7 1.10 1.5 3.6 0.9 6 8 1.25 1.6 - 1.0 - - V V V V MHz MHz
2003 Oct 02
26
Philips Semiconductors
Product specification
I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
SYMBOL S/NW PARAMETER weighted signal-to-noise ratio CONDITIONS MIN.
TDA9885; TDA9886
TYP. 59 -
MAX.
UNIT dB
weighted in accordance 56 with "CCIR 567"; see Fig.11; note 7 48 - - - - - - -2 0.8 -
S/NUW VIF-AGC; note 12 tresp(inc)
unweighted signal-to-noise ratio note 7
52
- - - - - - - -10 3.5 -
dB
AGC response time to an increasing VIF step
negative modulation; 20 dB; note 13 positive modulation; 20 dB; note 13
4 2.6 3 890 2.6 143 -6 - -80
ms ms ms ms ms/dB ms/dB dB V dB/V
tresp(dec)
AGC response time to a decreasing VIF step
negative modulation; 20 dB; note 13 positive modulation; 20 dB; note 13 L standard; fast mode L standard; normal mode; note 13
Vi(VIF) VVAGC CRstps
VIF amplitude step for activating L standard AGC fast mode gain control voltage range control steepness see Fig.7 definition: GVIF/VVAGC; VVAGC = 2 to 3 V see Tables 5 and 6
Vth(VIF) PIN VAGC Ich(max) Ich(add)
threshold voltage for high level VIF input
120
200
320
V
maximum charge current additional charge current
L standard
-
100 100
- -
A nA
L standard: in the event - of missing VITS pulses and no white video content L standard; normal mode L standard; fast mode - -
Idch
discharge current
35 1.8
- - 5
nA A mV
Tuner AGC (pin TAGC); see Figs 7 to 9 Vi(VIF)(start1)(rms) VIF input signal voltage for minimum starting point of tuner takeover at pins VIF1 and VIF2 (RMS value) VIF input signal voltage for maximum starting point of tuner takeover at pins VIF1 and VIF2 (RMS value) ITAGC = 120 A; - RTOP = 22 k or no RTOP and -15 dB via I2C-bus (see Table 13) ITAGC = 120 A; RTOP = 0 or no RTOP and +15 dB via I2C-bus (see Table 13) 45 2
Vi(VIF)(start2)(rms)
90
-
mV
2003 Oct 02
27
Philips Semiconductors
Product specification
I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
SYMBOL QVTOP PARAMETER tuner takeover point accuracy CONDITIONS ITAGC = 120 A; RTOP = 10 k or no RTOP and 0 dB via I2C-bus (see Table 13) ITAGC = 120 A from external source ITAGC = 450 A 7 MIN.
TDA9885; TDA9886
TYP. 17
MAX. 43
UNIT mV
QVTOP/T Vo Vsat Isink
takeover point variation with temperature permissible output voltage saturation voltage sink current
- - -
0.03 - - - 600 5
0.07 8.8 0.5 0.75 750 8
dB/K V V A A dB
no tuner gain reduction; - VTAGC = 8.8 V maximum tuner gain reduction; VTAGC = 1 V 450 3
GIF
IF slip by automatic gain control tuner gain current from 20 % to 80 %
AFC circuit (pin AFC); see Fig.10; notes 14 and 15 Vsat(ul) Vsat(ll) Io(source) Io(sink) AFCstps QfVIF(a) QfVIF(d) upper limit saturation voltage lower limit saturation voltage output source current output sink current AFC control steepness analog accuracy of AFC circuit digital accuracy of AFC circuit via I2C-bus definition: IAFC/fVIF IAFC = 0; fREF = 4 MHz IAFC = 0; fREF = 4 MHz; 1 digit = 25 kHz FM mode; -3 dB at intercarrier output pin SIOMAD AM mode; -3 dB at AF output pin AUD Vi(max)(rms) maximum input voltage (RMS value) FM mode; +1 dB at intercarrier output pin SIOMAD AM mode; +1 dB at AF output pin AUD Vi(ovl)(rms) GSIF(cr) BSIF(-3dB)(ll) BSIF(-3dB)(ul) Ri(dif) Ci(dif) VI overload input voltage (RMS value) SIF gain control range lower limit -3 dB SIF bandwidth upper limit -3 dB SIF bandwidth differential input resistance differential input capacitance DC input voltage note 3 note 3 note 2 FM and AM mode; see Fig.9 VP - 0.6 VP - 0.3 - - 160 160 0.85 -20 -20 - 1 digit - 0.3 200 200 1.05 - - 0.6 240 240 1.25 +20 V V A A A/kHz kHz
+20 kHz + 1 digit V
SIF amplifier (pins SIF1 and SIF2) Vi(SIF)(rms) SIF input voltage sensitivity (RMS value) 30 70
- 50
70 70
100 -
V mV
80 - 60 - - - - -
140 - 66 15 80 2 3 1.93
- 320 - - - - - -
mV mV dB MHz MHz k pF V
2003 Oct 02
28
Philips Semiconductors
Product specification
I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
SYMBOL SIF-AGC detector tresp AGC response time to an increasing or decreasing SIF step of 20 dB FM or AM fast step increasing decreasing AM slow step increasing decreasing Single reference QSS intercarrier mixer (pin SIOMAD) Vo(intc)(rms) IF intercarrier output level (RMS value) QSS mode; SC1; SC2 off L standard; without modulation intercarrier mode; PC/SC1 = 20 dB; SC2 off; note 16 Bintc(-3dB)(ul) Vr(SC)(rms) upper limit -3 dB intercarrier bandwidth residual sound carrier (RMS value) fundamental wave and harmonics QSS mode intercarrier mode Vr(PC)(rms) residual picture carrier (RMS value) fundamental wave and harmonics QSS mode intercarrier mode H Ro VO Ibias(int) Io(sink)(max) Io(source)(max) Io(source) suppression of video signal harmonics output resistance DC output voltage internal DC bias current for emitter follower maximum AC output sink current maximum AC output source current DC output source current MAD2 activated; note 17 intercarrier mode; fvideo = 5 MHz note 3 - - 35 - - 0.90 0.6 0.6 0.75 - - 90 90 - - - - - PARAMETER CONDITIONS MIN.
TDA9885; TDA9886
TYP.
MAX.
UNIT
8 25 80 250
- - - - 180 180 -
ms ms ms ms
140 140 75
mV mV mV
12
15
-
MHz
2 2
5 5
mV mV
2 5 40 - 2 1.15 0.8 0.8 0.93
5 20 - 30 - - - - 1.20
mV mV dB V mA mA mA mA
2003 Oct 02
29
Philips Semiconductors
Product specification
I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
SYMBOL PARAMETER CONDITIONS MIN.
TDA9885; TDA9886
TYP.
MAX.
UNIT
FM-PLL demodulator; notes 15 and 18 to 22 SOUND INTERCARRIER OUTPUT (PIN SIOMAD) VFM(rms) IF intercarrier level for gain controlled operation of FM-PLL (RMS value) IF intercarrier level for lock-in of PLL (RMS value) IF intercarrier level for FM carrier detect (RMS value) sound intercarrier operating FM frequencies see Table 6 see Table 14 corresponding PC/SC ratio at input pins VIF1 and VIF2 is 7 to 47 dB 3.2 - 320 mV
VFM(lock)(rms) VFM(det)(rms) fFM
- - - - - -
- - 4.5 5.5 6.0 6.5
2 2.3 - - - - 600 650 -
mV mV MHz MHz MHz MHz
AUDIO OUTPUT (PIN AUD) Vo(AF)(rms) AF output voltage (RMS value) 25 kHz FM deviation; 75 s de-emphasis 27 kHz FM deviation; 50 s de-emphasis Vo(AF)(cl)(rms) Vo(AF)/T THD fAF AF output clipping level (RMS value) AF output voltage variation with temperature total harmonic distortion frequency deviation THD < 1.5 %; note 19 -6 dB AF output via I2C-bus; note 19 BAF(-3dB) -3 dB AF bandwidth THD < 1.5 % 400 430 1.3 - - - - 500 540 1.4 mV mV V
3 x 10-3 7 x 10-3 dB/K 0.15 - - 100 0.50 55 110 - % kHz kHz kHz
without de-emphasis; 80 measured with FM-PLL filter of Fig.23 52
S/NW(AF)
weighted signal-to-noise ratio of FM-PLL only; audio signal 27 kHz FM deviation; 50 s de-emphasis black picture; see Fig.19
56
-
dB
50 -
56 -
- 2
dB mV
Vr(SC)(rms)
residual sound carrier (RMS value) AM suppression of FM demodulator
fundamental wave and harmonics; without de-emphasis referenced to 27 kHz FM deviation; 50 s de-emphasis; AM: f = 1 kHz; m = 54 % fripple = 70 Hz; see Fig.6
AM(sup)
40
46
-
dB
PSRRFM
power supply ripple rejection
14
20
-
dB
2003 Oct 02
30
Philips Semiconductors
Product specification
I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
SYMBOL PARAMETER CONDITIONS MIN.
TDA9885; TDA9886
TYP. - 60 60 55 55 16 64 3.3 4
MAX.
UNIT
FM-PLL FILTER (PIN FMPLL) Vloop Io(source)(PD)(max) Io(sink)(PD)(max) Io(source)(DAH) Io(sink)(DAH) tW(DAH) Tcy(DAH) KO(FM) KD(FM) Audio amplifier DE-EMPHASIS NETWORK (PIN DEEM) Ro output resistance 50 s de-emphasis; see Table 12 75 s de-emphasis; see Table 12 VAF(rms) VO Vdec IL Ich(max) Idch(max) Ro VO(AUD) RL RL(DC) CL BAF(-3dB)(ul) BAF(-3dB)(ll) mute 2003 Oct 02 audio signal (RMS value) DC output voltage fAF = 400 Hz; VAUD = 500 mV 4.4 6.6 - - dependent on fFM intercarrier frequency VO(AUD) < 50 mV 1.5 - 1.15 1.15 - - AC-coupled 10 100 - 150 note 20 via I2C-bus 31 - 70 5.0 7.5 170 2.37 - - 1.50 1.50 - 2.37 - - - - - 75 5.6 8.4 - - 3.3 25 1.85 1.85 k k mV V DC loop voltage maximum phase detector output source current maximum phase detector output sink current output source current of digital acquisition help output sink current of digital acquisition help pulse width of digital acquisition help current cycle time of digital acquisition help VCO steepness phase detector steepness 1.5 - - - - - - definition: fFM/VFMPLL - definition: IFMPLL/FM - 3.3 - - - - - - - - V A A A A s s MHz/V A/rad
AF DECOUPLING (PIN AFD) DC decoupling voltage leakage current maximum charge current maximum discharge current V nA A A V k k nF kHz Hz dB
AUDIO OUTPUT (PIN AUD) output resistance DC output voltage load resistance DC load resistance load capacitance upper limit -3 dB AF bandwidth of audio amplifier lower limit -3 dB AF bandwidth of audio amplifier mute attenuation of AF signal note 3 300 - - - 1.5 - 20 -
Philips Semiconductors
Product specification
I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
SYMBOL Vjump PARAMETER DC jump voltage for switching AF output to mute state or vice versa CONDITIONS activated by digital acquisition help or via I2C-bus mute - MIN.
TDA9885; TDA9886
TYP. 50
MAX. 150
UNIT mV
FM operation; notes 21 and 23 INTERCARRIER AF PERFORMANCE; note 24 S/NW weighted signal-to-noise ratio PC/SC ratio is 21 to 27 dB at pins VIF1 and VIF2 black picture white picture 6 kHz sine wave (black-to-white modulation) sound carrier subharmonics; f = 2.75 MHz 3 kHz SINGLE REFERENCE QSS AF PERFORMANCE; notes 25 and 26 S/NW(SC1) weighted signal-to-noise ratio for SC1 PC/SC1 ratio at pins VIF1 and VIF2; 27 kHz (54 % FM deviation); "CCIR 468" black picture white picture 6 kHz sine wave (black-to-white modulation) 40 - - dB 50 45 40 56 51 46 - - - dB dB dB
35
40
-
dB
53 50 44
58 53 48
- - -
dB dB dB
250 kHz square wave 40 (black-to-white modulation) sound carrier subharmonics; f = 2.75 MHz 3 kHz sound carrier subharmonics; f = 2.87 MHz 3 kHz 45
45
-
dB
51
-
dB
46
52
-
dB
2003 Oct 02
32
Philips Semiconductors
Product specification
I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
SYMBOL S/NW(SC2) PARAMETER weighted signal-to-noise ratio for SC2 CONDITIONS PC/SC2 ratio at pins VIF1 and VIF2; 27 kHz (54 % FM deviation); "CCIR 468" black picture white picture 6 kHz sine wave (black-to-white modulation) MIN. 40
TDA9885; TDA9886
TYP. - -
MAX.
UNIT dB
48 46 42
55 51 46
- - -
dB dB dB
250 kHz square wave 29 (black-to-white modulation) sound carrier subharmonics; f = 2.75 MHz 3 kHz sound carrier subharmonics; f = 2.87 MHz 3 kHz AM operation L STANDARD (PIN AUD); see Figs 20 and 21; note 27 Vo(AF)(rms) THD BAF(-3dB) S/NW(AF) VO(AUD) PSRRAM VI Ri Rxtal Cx fref fref Vref(rms) Ro(ref) CK AF output voltage (RMS value) total harmonic distortion -3 dB AF bandwidth weighted signal-to-noise ratio of in accordance with audio signal "CCIR 468" DC potential voltage power supply ripple rejection see Fig.6 54 % modulation 54 % modulation 400 - 100 45 - 20 44
34
-
dB
50
-
dB
45
51
-
dB
500 0.5 125 50 2.37 26
600 1.0 - - - - 2.9 - 200 - - 0.1 400 4.7 -
mV % kHz dB V dB
Reference frequency input (pin REF) DC input voltage input resistance resonance resistance of crystal pull-up/down capacitance reference signal frequency tolerance of reference signal frequency reference signal voltage (RMS value) output resistance of reference signal source decoupling capacitance to operation as input external reference signal source terminal note 3 operation as crystal oscillator note 28 note 29 note 15 operation as input terminal 2.3 - - - - - 80 - 22 2.6 5 - - 4 - - - 100 V k pF MHz % mV k pF
2003 Oct 02
33
Philips Semiconductors
Product specification
I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
SYMBOL PARAMETER CONDITIONS MIN.
TDA9885; TDA9886
TYP.
MAX.
UNIT
I2C-bus transceiver (pins SDA and SCL); notes 30 and 31 fSCL VIH VIL IIH IIL VOL Io(sink) Io(source) VOL VOH Io(sink) Io(sink/source)(max) Notes 1. Values of video and sound parameters can be decreased at VP = 4.5 V. 2. Level headroom for input level jumps during gain control setting. 3. This parameter is not tested during the production and is only given as application information for designing the receiver circuit. 4. Loop bandwidth BL = 70 kHz (damping factor d = 1.9; calculated with sync level within gain control range). Calculation of the VIF-PLL filter can be done by use of the following formula: 1 BL -3dB = ------ K O K D R , valid for d 1.2 2 1 d = -- R K O K D C , 2 where: rad Hz A KO is the VCO steepness ------- or 2 ------ ; KD is the phase detector steepness ------- ; V - rad V R is the loop resistor; C is the loop capacitor; BL-3dB is the loop bandwidth for -3 dB; d is the damping factor. 5. Vi(VIF) = 10 mV (RMS); f = 1 MHz (VCO frequency offset related to picture carrier frequency); white picture video modulation. 6. Condition: luminance range (5 steps) from 0 % to 100 %. 7. S/N is the ratio of black-to-white amplitude to the black level noise voltage (RMS value on pin CVBS). B = 5 MHz (B/G, I and D/K standard). Noise analyzer setting: 200 kHz high-pass and SC-trap switched on. 8. The intermodulation figures are defined for: V 0 at 4.4 MHz a) f = 1.1 MHz (referenced to black and white signal) as IM = 20 log ------------------------------------- + 3.6 dB V 0 at 1.1 MHz V 0 at 4.4 MHz b) f = 3.3 MHz (referenced to colour carrier) as IM = 20 log ------------------------------------- V 0 at 3.3 MHz 2003 Oct 02 34 SCL clock frequency HIGH-level input voltage LOW-level input voltage HIGH-level input current LOW-level input current LOW-level output voltage output sink current output source current IOL = 3 mA VP = 0 V VP = 0 V IOL = 2 mA (sink current) 0 3 -0.3 -10 -10 - - - - - - pin OP2 functions as VIF-AGC output - - - - - - - - - - - - - 400 VCC +1.5 +10 +10 0.4 10 10 kHz V V A A V A A V V mA A
Output ports (pins OP1 and OP2); note 32 LOW-level output voltage HIGH-level output voltage output sink current maximum output sink or source current 0.4 6 2 10
Philips Semiconductors
Product specification
I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
TDA9885; TDA9886
9. Measurements taken with SAW filter M1963M (sound shelf: 20 dB); loop bandwidth BL = 70 kHz. a) Modulation Vestigial Side-Band (VSB); sound carrier off; fvideo > 0.5 MHz. b) Sound carrier on; fvideo = 10 kHz to 10 MHz. 10. AC load; CL < 20 pF and RL > 1 k. The sound carrier frequencies (depending on TV standard) are attenuated by the integrated sound carrier traps (see Figs 13 to 18; H (s) is the absolute value of transfer function). 11. The sound carrier trap can be bypassed by switching the I2C-bus. In this way the full composite video spectrum appears at pin CVBS. The amplitude is 1.1 V (p-p). 12. If selected by the I2C-bus, the VIF-AGC voltage can be monitored at pin OP2, and pin OP1 can be used as input. In this case, both pins cannot be used for the normal port function. 13. The response time is valid for a VIF input level range from 200 V to 70 mV. 14. To match the AFC output signal to different tuning systems a current source output is provided. The test circuit is given in Fig.10. The AFC slope (voltage per frequency) can be changed by resistors R1 and R2. 15. The tolerance of the reference frequency determines the accuracy of the VIF-AFC, FM demodulator centre frequency and maximum FM deviation. 16. The intercarrier output signal at pin SIOMAD can be calculated by the following formula taking into account the internal video signal with 1.1 V (p-p) as a reference: 1 r V o(intc)(rms) = 1.1 x ---------- x 10 V 22 V i(SC) 1 and r = ----- x ------------- ( dB ) + 6 dB 3 dB 20 V i(PC) where: V i ( SC ) 1 ---------- is the correction term for RMS value, --------------- ( dB ) is the sound-to-picture carrier ratio at pins VIF1 and VIF2 V i ( PC ) 22 in dB, 6 dB is the correction term of internal circuitry and 3 dB is the tolerance of video output and intercarrier output Vo(intc)(rms). 17. For normal operation (with the I2C-bus) no DC load at pin SIOMAD is allowed. The second module address (MAD2) will be activated by the application of a 2.2 k resistor between pin SIOMAD and ground. If this MAD2 is activated, also the power-on set-up state activates a VIF frequency of 58.75 MHz. 18. SIF input level is 10 mV (RMS); VIF input level is 10 mV (RMS) unmodulated. 19. Measured with an FM deviation of 25 kHz and the typical AF output voltage of 500 mV (RMS). The AF output signal can be attenuated by 6 dB to 250 mV (RMS) via the I2C-bus. For handling a frequency deviation of more than 55 kHz, the AF output signal has to be reduced in order to avoid clipping (THD < 1.5 %). 20. The lower limit of the audio bandwidth depends on the value of the capacitor at pin AFD. A value of CAF = 470 nF leads to fAF(-3dB) 20 Hz and CAF = 220 nF leads to fAF(-3dB) 40 Hz. 21. For all S/N measurements the VIF modulator in use has to meet the following specifications: a) Incidental phase modulation for black-to-white jump less than 0.5 degrees. b) QSS AF performance, measured with the television demodulator AMF2 (audio output, weighted S/N ratio) better than 60 dB (at deviation 27 kHz) for 6 kHz sine wave black-to-white video modulation. c) Picture-to-sound carrier ratio PC/SC1 = 13 dB (transmitter).
2003 Oct 02
35
Philips Semiconductors
Product specification
I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
TDA9885; TDA9886
22. Calculation of the loop filter parameters can be done approximately using the following formulae: 1 KO KD f o = ------ -------------2 C P 1 = ----------------------------------2R K O K D C P BL -3dB = f o ( 1.55 - ) The formulae are only valid under the following conditions: 1 and CS > 5CP where: rad Hz KO is the VCO steepness ------- or 2 ------ ; V - V A KD is the phase detector steepness ------- ; rad R is the loop resistor; CS is the series capacitor; CP is the parallel capacitor; fo is the natural frequency of PLL; BL-3dB is the loop bandwidth for -3 dB; is the damping factor. For examples, see Table 19. 23. The PC/SC ratio is calculated as the addition of TV transmitter PC/SC1 ratio and SAW filter PC/SC1 ratio. This PC/SC ratio is necessary to achieve the S/NW values as noted. A different PC/SC ratio will change these values. 24. Measurements taken with SAW filter G1984 (Siemens) for vision and sound IF (sound shelf: 14 dB). Picture-to-sound carrier ratio of transmitter PC/SC = 13 dB. Input level on pins VIF1 and VIF2 of Vi(SIF) = 10 mV (RMS) sync level, 27 kHz FM deviation for sound carrier, fAF = 400 Hz. Measurements in accordance with "CCIR 468". De-emphasis is 50 s. 25. The QSS signal output on pin SIOMAD is analysed by a test demodulator TDA9820. The S/N ratio of this device is more than 60 dB, related to a deviation of 27 kHz, in accordance with "CCIR 468". 26. Measurements taken with SAW filter K3953 for vision IF (suppressed sound carrier) and K9453 for sound IF (suppressed picture carrier). Input level Vi(SIF) = 10 mV (RMS), 27 kHz (54 % FM deviation). 27. Measurements taken with SAW filter K9453 (Siemens) for AM sound IF (suppressed picture carrier). 28. The value of Cx determines the accuracy of the resonance frequency of the crystal. It depends on the type of crystal used. 29. Pin REF is able to operate as a 1-pin crystal oscillator input as well as an external reference signal input, e.g. from the tuning system. 30. The SDA and SCL lines will not be pulled down if VCC is switched off. 31. The AC characteristics are in accordance with the I2C-bus specification for fast mode (maximum clock frequency is 400 kHz). Information about the I2C-bus can be found in the brochure "The I2C-bus and how to use it" (order number 9398 393 40011). 32. Port P1 and port P2 are open-collector outputs.
2
2003 Oct 02
36
Philips Semiconductors
Product specification
I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
Table 19 Examples to note 22 (FM-PLL filter) BL-3dB (kHz) 100 160 CS (nF) 10 10 CP (pF) 390 150
TDA9885; TDA9886
R (k) 5.6 9.1
0.5 0.5
Table 20 Input frequencies and carrier ratios DESCRIPTION VIF carrier SIF carrier Picture-to-sound carrier ratio SYMBOL fPC fSC1 fSC2 SC1 SC2 B/G STANDARD 38.9 33.4 33.158 13 20 M/N STANDARD 45.75 or 58.75 41.25 or 54.25 - 7 - L STANDARD 38.9 32.4 - 10 - L ACCENT STANDARD 33.9 40.4 - 10 - UNIT MHz MHz MHz dB dB
2003 Oct 02
37
Philips Semiconductors
Product specification
I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
TDA9885; TDA9886
handbook, full pagewidth
trap bypass mode normal mode 2.72 V 2.6 V 3.41 V 3.20 V zero carrier level white level
1.83 V
1.80 V
black level
1.5 V
1.20 V
sync level
MHC115
Fig.5 Typical video signal levels on output pin CVBS (sound carrier off).
handbook, full pagewidth
VP VP = 5 V (V) 5 100 mV
TDA9885 TDA9886
fripple = 70 Hz
MHC114
t (s)
Fig.6 Ripple rejection condition.
2003 Oct 02
38
Philips Semiconductors
Product specification
I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
TDA9885; TDA9886
MHC116
handbook, full pagewidth
VVAGC (V) 4
I TAGC (A) 600 500 400
3 300 200 2
(1) (2) (3) (4)
100 0
1 30
40
50
60
70
80
90
100
110
120
Vi(VIF) (dBV) (1) VVAGC is VIF-AGC voltage and can only be measured at pin OP2 controlled by the I2C-bus (see Table 15). (2) ITAGC is tuner current in TV mode with RTOP = 22 k or setting via I2C-bus at -15 dB. (3) ITAGC is tuner current in TV mode with RTOP = 10 k or setting via I2C-bus at 0 dB. (4) ITAGC is tuner current in TV mode with RTOP = 0 k or setting via I2C-bus at +15 dB.
Fig.7 Typical VIF and tuner AGC characteristic.
handbook, halfpage
110
MHB159
MHC117
Vi(VIF) (dBV)
handbook, halfpage
5
VSAGC (V) 4
100
90 3
(1)
80
(2)
2 70
60 0 4 8 12 16 20 24 RTOP (k)
1 30 50 70 90 110 130 Vi(SIF) (dBV)
(1) FM mode. (2) AM mode.
Fig.8
Typical tuner takeover point as a function of resistor RTOP.
Fig.9 Typical SIF-AGC characteristic.
2003 Oct 02
39
Philips Semiconductors
Product specification
I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
TDA9885; TDA9886
handbook, full pagewidth
lock range without SAW filter AFC window 5 VAFC (V) 4 -100 3 0 2 +100 1 +200 0 36 37 38 38.9 38.71 39.09 40 f (MHz)
MHC113
IAFC (A) -200
VP
TDA9885 21 TDA9886 (23)
IAFC
R1 22 k VAFC R2 22 k
41
Pin numbers for TDA9885HN and TDA9886HN in parenthesis.
Fig.10 Typical analog AFC characteristic.
MHC112
handbook, halfpage
80
handbook, halfpage
3.2 dB 10 dB 13.2 dB 21 dB
S/N (dB) 60
13.2 dB 21 dB
40 SC CC PC SC CC PC
BLUE
20
YELLOW
MHA739
0 30
50
70
90 Vi(VIF) (dBV)
110
SC is sound carrier, with respect to sync level. CC is chrominance carrier, with respect to sync level. PC is picture carrier, with respect to sync level. The sound carrier levels are take into account a sound shelf attenuation of 14 dB (SAW filter G1984M).
Fig.11 Typical signal-to-noise ratio as a function of VIF input voltage.
Fig.12 Input signal conditions.
2003 Oct 02
40
Philips Semiconductors
Product specification
I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
TDA9885; TDA9886
MHC122
handbook, full pagewidth
10 H (s) (dB) 0
-10
-20
-30
minimum requirements
-40
2
2.5
3
3.5
4
4.5 f (MHz) 5
Fig.13 Typical amplitude response for sound trap at M/N standard (including Korea).
handbook, full pagewidth
400 group delay (ns) 300
MHB167
200 ideal characteristic due to pre-correction in the transmitter 100
0
minimum requirements
-100
0
0.5
1
1.5
2
2.5
3
3.5
f (MHz)
4
Overall delay is not shown, here the maximum ripple is specified.
Fig.14 Typical group delay for sound trap at M/N standard.
2003 Oct 02
41
Philips Semiconductors
Product specification
I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
TDA9885; TDA9886
handbook, full pagewidth
10 H (s) (dB) 0
MHB168
-10
-20
-30
minimum requirements
-40
4
4.5
5
5.5
6
6.5 f (MHz) 7
Fig.15 Typical amplitude response for sound trap at B/G standard.
handbook, full pagewidth
400 group delay (ns) 300
MHB169
200
ideal characteristic due to pre-correction in the transmitter
100
0
minimum requirements
-100
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5 f (MHz) 5
Overall delay is not shown, here the maximum ripple is specified.
Fig.16 Typical group delay for sound trap at B/G standard.
2003 Oct 02
42
Philips Semiconductors
Product specification
I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
TDA9885; TDA9886
MHC123
handbook, full pagewidth
10 H (s) (dB) 0
-10
-20
-30
minimum requirements
-40
4
4.5
5
5.5
6
6.5 f (MHz) 7
Fig.17 Typical amplitude response for sound trap at I standard.
MHB171
handbook, full pagewidth
10 H (s) (dB) 0
-10
-20
-30
minimum requirements
-40
4
4.5
5
5.5
6
6.5 f (MHz) 7
Fig.18 Typical amplitude response for sound trap at D/K standard.
2003 Oct 02
43
Philips Semiconductors
Product specification
I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
TDA9885; TDA9886
handbook, full pagewidth
10
MHC118
S/NW
0
(1)
(dB) -10 -20 -30 -40
(2)
-50 -60 -70
(3)
52
49
46
43
40
37
34
31
28
25
22
19
16
13
10
7
4
PC/SC ratio gain controlled operation of FM-PLL
(1) Signal. (2) Noise at H-picture (CCIR weighted quasi peak). (3) Noise at black picture (CCIR weighted quasi peak).
Conditions: PC/SC ratio measured at pins VIF1 and VIF2; via transformer; 27 kHz FM deviation; 50 s de-emphasis.
Fig.19 Audio signal-to-noise ratio as a function of picture-to-sound carrier ratio in intercarrier mode.
2003 Oct 02
44
Philips Semiconductors
Product specification
I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
TDA9885; TDA9886
handbook, full pagewidth
10
MHC119
S/NW
0
(1)
(dB) -10 -20 -30 -40
(2)
-50 -60 -70
30
45
60
75
90
Vi (dBV)
105
(1) Signal. (2) Noise.
Condition: m = 54 %.
Fig.20 Typical audio signal-to-noise ratio as a function of input signal at AM standard.
handbook, full pagewidth
1.5
MHC120
THD (%)
1.0
0.5
0 10 -2
10 -1
1
10
fAF (kHz)
102
CAGC = 2.2 F; m = 54 %.
Fig.21 Typical total harmonic distortion as a function of audio frequency at AM standard.
2003 Oct 02
45
Philips Semiconductors
Product specification
I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
TDA9885; TDA9886
handbook, full pagewidth
140
MHC121
10 IF signals RMS value (V) video 2 V (p-p) 1
antenna input (dBV)
120
(1)
100 SAW insertion loss 20 dB
10-1
IF slip 6 dB 80 tuning gain control range 70 dB VIF AGC 60
10-2 (TOP)
10-3 0.66 x 10-3
SAW insertion loss 20 dB 40 40 dB RF gain 10-4
20
10-5 0.66 x 10-5
10 VHF/UHF tuner tuner VIF SAW filter VIF amplifier, demodulator and video TDA9885, TDA9886
(1) Depends on TOP.
Fig.22 Front-end level diagram.
2003 Oct 02
46
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dth
2003 Oct 02 47
13 TEST AND APPLICATION INFORMATION
Philips Semiconductors
I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
SIF input
AFC output 1:1 22 k 100 nF
VP 1.5 nF
VIF-PLL filter (2)
CVBS output
external reference
tuner AGC output
150
100 pF
4 MHz Cx
51
R3 150 k
(1) R2
150 k
22 k
220 nF VP 20 (22)
470 nF AGND 18 (20) CVBS 17 (18) VAGC (3) 16 REF 15 (16) TAGC 14 (15) n.c. 13 (6, 12, 13, 14, 17, 19, 25, 28, 29, 32)
SIF2 24 (27)
SIF1 23 (26)
OP2 22 (24)
AFC 21 (23)
VPLL 19 (21)
TDA9885 TDA9886
(30) 1 VIF1 VIF input (31) 2 VIF2 (1) 3 OP1 (2) 4 FMPLL (3) 5 DEEM (4) 6 AFD (5) 7 DGND (7) 8 AUD (8) 9 TOP (9) 10 SDA (10) 11 SCL
(11) 12 SIOMAD
1:1 10 nF 5.6 k 390 pF 10 nF 470 nF 22 k MAD select R1 2.2 k
(1)
51
FM-PLL filter
audio output
intercarrier output
MHC124
TDA9885; TDA9886
Pin numbers for TDA9885HN and TDA9886HN in parenthesis. (1) Optional for I2C-bus address selection. Option R2 and R3 not used R2 = R3 = 150 k R1 not used 1000 011 (R/W) 1001 011 (R/W) R1 = 2.2 k 1000 010 (R/W) 1001 010 (R/W)
Product specification
(2) Different VIF loop filter in comparison with the application circuit due to different input characteristics (SAW filter or transformer). (3) Not connected for TDA9885.
Fig.23 Test circuit.
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book, full pagewidth
2003 Oct 02
680 k 220 k BC847C BA277 5V BA277 1 2 BA277 6.8 k 6.8 k SAW FILTER K9456 3 SIF2 24 (27) 10 nF 5V SIF1 23 (26) OP2 (1) 22 (24) AFC 21 (23) VP 20 (22) 5 4 10 nF 22 k 22 k (30) 1 VIF1 IF input (31) 2 VIF2 (1) 3 OP1 (2) 4 FMPLL (3) 5
Philips Semiconductors
I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
CVBS output
fref
tuner AGC
(3)
10 F 1.5 nF 330
75 220
12 k 5V 100 k 47 F
BC847
10 nF
220 nF
470 nF AGND 18 (20) CVBS 17 (18) VAGC (2) 16
100 pF REF 15 (16)
VPLL 19 (21)
TAGC 14 (15)
n.c. 13 (6, 12, 13, 14, 17, 19, 25, 28, 29, 32)
TDA9885 TDA9886
(4) 6 AFD (5) 7 DGND (7) 8 AUD (8) 9 TOP (9) 10 SDA 100 1 51 2 SAW FILTER K3953 3 5 4 390 pF 10 nF 5.6 k AF output positive supply I 2C-bus controller 10 nF 470 nF (10) 11 SCL 100
48
(11) 12 SIOMAD
DEEM
(3)
I 2C-bus
intercarrier output
TDA9885; TDA9886
MHC125
Product specification
Pin numbers for TDA9885HN and TDA9886HN in parenthesis. (1) If pin OP2 outputs VIF-AGC voltage, then pin OP1 can be used for SAW switching. (2) Not connected for TDA9885. (3) Optional measures to improve ESD performance within a TV-set application.
Fig.24 Application circuit.
Philips Semiconductors
Product specification
I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
14 PACKAGE OUTLINES SO24: plastic small outline package; 24 leads; body width 7.5 mm
TDA9885; TDA9886
SOT137-1
D
E
A X
c y HE vMA
Z 24 13
Q A2 A1 pin 1 index Lp L 1 e bp 12 wM detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.1 A1 0.3 0.1 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 15.6 15.2 0.61 0.60 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.05 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z
(1)
0.9 0.4 0.035 0.016
0.012 0.096 0.004 0.089
0.019 0.013 0.014 0.009
0.419 0.043 0.055 0.394 0.016
8o 0o
Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT137-1 REFERENCES IEC 075E05 JEDEC MS-013 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
2003 Oct 02
49
Philips Semiconductors
Product specification
I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
TDA9885; TDA9886
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm
SOT340-1
D
E
A X
c y HE vMA
Z 24 13
Q A2 pin 1 index A1 (A 3) Lp L 1 e bp 12 wM detail X A
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 8.4 8.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 0.8 0.4 8 0o
o
Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT340-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
2003 Oct 02
50
Philips Semiconductors
Product specification
I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
TDA9885; TDA9886
HVQFN32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm
SOT617-3
D
B
A
terminal 1 index area
A E A1 c
detail X
C e1 e 9 L 8 17 e
1/2 e
b 16
vMCAB wM C
y1 C
y
Eh
1/2 e
e2
1 terminal 1 index area 32 Dh 0 DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 5.1 4.9 Dh 3.75 3.45 E (1) 5.1 4.9 Eh 3.75 3.45 25
24
X
2.5 scale e 0.5 e1 3.5 e2 3.5 L 0.5 0.3
5 mm
v 0.1
w 0.05
y 0.05
y1 0.1
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT617-3 REFERENCES IEC --JEDEC MO-220 JEITA --EUROPEAN PROJECTION ISSUE DATE 02-04-18 02-10-22
2003 Oct 02
51
Philips Semiconductors
Product specification
I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
15 SOLDERING 15.1 Introduction to soldering surface mount packages
TDA9885; TDA9886
To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 15.4 Manual soldering
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 15.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept: * below 220 C (SnPb process) or below 245 C (Pb-free process) - for all BGA and SSOP-T packages - for packages with a thickness 2.5 mm - for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages. * below 235 C (SnPb process) or below 260 C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times. 15.3 Wave soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems.
2003 Oct 02
52
Philips Semiconductors
Product specification
I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
15.5
TDA9885; TDA9886
Suitability of surface mount IC packages for wave and reflow soldering methods PACKAGE(1) SOLDERING METHOD WAVE REFLOW(2) suitable suitable suitable suitable suitable not suitable
BGA, LBGA, LFBGA, SQFP, SSOP-T(3), TFBGA, VFBGA DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC(5), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP PMFP(8) Notes
not suitable not suitable(4)
suitable not not recommended(5)(6) recommended(7)
not suitable
1. For more detailed information on the BGA packages refer to the "(LF)BGA Application Note" (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 3. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. 4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 5. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 6. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 7. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 8. Hot bar or manual soldering is suitable for PMFP packages.
2003 Oct 02
53
Philips Semiconductors
Product specification
I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
16 DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development
TDA9885; TDA9886
DEFINITION This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data Qualification
III
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 17 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 18 DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2003 Oct 02
54
Philips Semiconductors
Product specification
I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
19 PURCHASE OF PHILIPS I2C COMPONENTS
TDA9885; TDA9886
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
2003 Oct 02
55
Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2003
SCA75
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753504/02/pp56
Date of release: 2003
Oct 02
Document order number:
9397 750 11443

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